RF technology to ease design of nanometer wireless chips
Cadence Design Systems has introduced Cadence Virtuoso Passive Component Designer, a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. The new technology puts passive component design into the hands of analog and RF designers developing fast and complex wireless SoCs and RFICs.
Starting from design specifications such as inductance, quality factor and frequency, the Virtuoso Passive Component Designer helps designers automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area, says the company.
A built-in accurate 3D full wave solver verifies the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turnaround time.
Virtuoso Passive Component Designer is optimized for 90- and 65-nanometer process nodes, supporting advanced design rules and CMP constraints such as dummy metal fills and slotting. In addition to the wide variety of supported inductor and transformer geometries, it allows the design teams to define their own custom geometries graphically or manually using parameterized cells, or Pcells.
“Inductors and transformers are critical components in our high frequency integrated circuit. They have high impact on chip area and performance,” said Hisaharu Miwa, general manager of the Design Technology Division, Renesas Technology Corp. “Our goal is to improve design productivity by considering the impact of inductors and transformers from the early design stages. We use Virtuoso Passive Component Designer because it addresses these challenges. Virtuoso Passive Component Designer provides an easy way to model and generate PDK components due to its integration in Virtuoso custom design platform and its accurate built-in electromagnetic solver.”
“This new FDK allows us to leverage advanced features of both UMC 65-nanometer process and the Cadence Virtuoso platform in our upcoming designs and helps us to meet time-to-market requirements,” said C. J. Hsieh, associate vice president of SoC Development and Service at Faraday.
“The rapid development of UMC’s 65-nanometer FDKs for the new Virtuoso technology underscores the importance of Virtuoso solutions among innovative mixed-signal and RF designers,” said Charlie Giorgetti, corporate vice president of Product Marketing at Cadence. “We look forward to working with UMC to enable further FDKs with the latest Virtuoso solutions in support of our mutual customers’ growing demand.”
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