IBM is using tiny rivers of water to cool computer chips that have circuits and components stacked on top of each other – a design the researchers say promises to advance Moore’s law, and significantly reduce energy consumed by data centres.

IBM researchers, in collaboration with the Fraunhofer Institute, Berlin, have created a prototype device that integrates the cooling system into the 3D chips by piping water directly between each layer in the stack. These so-called 3D chip stacks – which take chips and memory devices that traditionally sit side-by-side on a silicon wafer and stacks them together on top of one another – presents one of the most promising approaches to enhancing chip performance beyond its predicted limits.

This development follows IBM’s advance in chip-stacking technology in a manufacturing environment, which when compared to 2D chips, shortens the distance information on a chip needs to travel by up to 1000 times, and allows for the addition of up to 100 times more channels, or pathways for that information to flow.

Thomas Brunschwiler, project leader, IBM, explained: “As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that the conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance3D chip stacking, we need interlaying cooling.

“Until now nobody has demonstrated viable solutions to this problem.”

3D chip stacks would have an aggregated heat dissipation of close to 1kw – 10 times greater than the heat generated by a hotplate – with an area of 4cm2 and a thickness of about 1mm, with each layer possessing an additional barrier to heat removal.

The IBM team piped water into cooling structures 50 microns thick, between the individual chip layers in order to remove heat efficiently at the source. Using the superior thermophysical qualities of water, scientists were able to demonstrate a cooling performance of up to 180W/cm2 per layer for a stack with a typical footprint of 4cm2.

During experiments, scientists piped water through a 1 x 1cm test vehicle, consisting of a cooling layer between two dies or heat sources. The cooling layer measures 100 microns in height and is packed with 10,000 vertical interconnects per cm2.

The team overcame technical challenges in designing a system that maximises the water flow through the layers, yet hermetically seals the interconnects to prevent water from causing electrical shorts.

The individual layers were fabricated using existing methods, except for those which needed to be etched or drilled to allow for signal transmission from layer layer to the next. To insulate these, scientists left a silicon wall around each interconnect (also referred to as silicon vias) and added a fine layer of silicon oxide to insulate he electrical interconnects from the water. The structures had to be fabricated to an accuracy of 10 microns, 10 times more accurate than for interconnects and metallisations in current chips.

To assemble the individual layers, Bruschweiler, along with colleagues from the Fraunhofer Institute, developed a sophisticated thin-film soldering technique. Using this technique, scientists achieved the high quality precision and robustness needed to ensure thermal contacts to the required standard, and electrical contacts without shorts.

In the final setup, the assembled stack is placed in a silicon cooling container with water pumped in from one side. This flows between the individual chip layers before exiting on the other side.

Using simulations, scientists extrapolated the experimental results of their test vehicle to a 4cm2 chip stack and achieved a cooling performance of 180W/cm2.

In the future, Bruschweiler and this team hope to optimise cooling systems for even smaller chip dimensions and more interconnections. They also plan to investigate additional structures for hotspot cooling.