Researchers from the Massachusetts Institute of Technology have achieved a significant advance in nanoscale lithographic technology used in the manufacture of computer chips and other electronic devices, to make finer patterns of lines over larger areas than have been possible with other methods.

This new technique could pave the way for next-generation computer memory and integrated circuit-chips, as well as advanced solar cells and other devices.

The team has created lines around 25 nanometers wide, separated by 25nm spaces. In comparison, the most advanced commercially available computer chips today have a minimum feature size of 65nm, while Intel recently announced it would start manufacturing at 32nm minimum line width scale in 2009.

The MIT technique works without the chemically amplified resists, immersion lithography techniques and expensive lithography tools widely considered essential to work at this scale with optical lithography, making it economically attractive.

Periodic patterns at the nanoscale, while having many important scientific and commercial applications, are notoriously difficult to produce with low cost and high yield. The new method could make possible the commercialisation of many new nanotechnology inventions that may have been put aside due to a lack of a viable manufacturing method.

Mark Schattenburg and colleagues at MIT, used a technique known as interface lithography (IL) to generate the patterns, but they did so using a tool called a ‘nanoruler’.

Built by MIT graduate students, the nanoruler is designed to perform a particularly high precision variant of IL called scanning-beam interference lithography, or SBIL. This recently developed technique uses 100MHz sound waves, controlled by custom high-speed electronics, to diffract and frequency-shift the laser light, resulting in rapid patterning of large areas with unprecedented control over feature geometry.

While IL has been around for a while, the SBIL technique has enabled the precise and repeatable pattern registration and overlay over large areas, thanks to a new high precision phase detection algorithm developed by MIT graduate student Yong Zhao, and a novel image reversal process developed by fellow MIT graduate student Chih-Hao Chang.

Schattenburg explained: “What we’re finding is that control of the lithographic imaging process is no longer the limiting step. Material issues such as line sidewall roughness are now a major barrier to still-finer length scales. However, there are several new technologies on the horizon that have the potential for alleviating these problems. These results demonstrate that there’s still a lot of room left for scale shrinkage in optical lithography. We don’t seen any insurmountable roadblocks just yet.”