Researchers at Purdue University have developed a new technology designed to meet the cooling needs of future high-performance chips.

Using ‘microjets’, the researchers have been able to achieve a cooling capacity of 1,000 watts per square centimetre.

The cooling system is made of groves narrower than a millimetre wide. These channels are formed on top of a chip and covered with a metal plate containing tiny holes. The cooling liquid, hydroflurocarbon, is pumped through the holes in microjets, allowing the liquid to flow along the channels and cool the chip. As the liquid is heated by the hot chip inside the channels, it bubbles and momentarily becomes a vapour, facilitating the cooling process.

Issam Mudawar, a professor of mechanical engineering at Purdue University, and leader of the research project, explained: “In many ways, progress in the computer and electronics industries is becoming increasingly defined by how well you can cool chips.

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IBM is using tiny rivers of water to cool computer chips that have circuits and components stacked on top of each other – a design the researchers say promises to advance Moore’s law, and significantly reduce energy consumed by data centres.

IBM researchers, in collaboration with the Fraunhofer Institute, Berlin, have created a prototype device that integrates the cooling system into the 3D chips by piping water directly between each layer in the stack. These so-called 3D chip stacks – which take chips and memory devices that traditionally sit side-by-side on a silicon wafer and stacks them together on top of one another – presents one of the most promising approaches to enhancing chip performance beyond its predicted limits.

This development follows IBM’s advance in chip-stacking technology in a manufacturing environment, which when compared to 2D chips, shortens the distance information on a chip needs to travel by up to 1000 times, and allows for the addition of up to 100 times more channels, or pathways for that information to flow.

Thomas Brunschwiler, project leader, IBM, explained: “As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that the conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance3D chip stacking, we need interlaying cooling.

“Until now nobody has demonstrated viable solutions to this problem.”

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