Archive for the ‘transistor’ tag
Panasonic and Renesas Technology to develop SoCs at 32-nm process node
Panasonic Corporation and Renesas Technology are to collaborate on the development of elemental process technologies for systems-on-a-chip (SoCs) of the next generation 32nm node. The two companies are confident that their 32nm node transistor technology and other advances could soon be applied to products in mass production.
The companies predict that the SoCs at the 32nm node will deliver lower cost and improved performance enabled by miniaturisation of their design rules, but currently many technical issues stand in the way. In particular, new materials and technologies are needed to break through barriers to further integration, such as transistor gate leakage and inconsistent electrical characteristic problems, which are often found in existing technologies. Introducing new materials is technically difficult, however, the technology challenges in achieving acceptable transistor performance at the 32nm node are more formidable than they were at previous-generation process nodes.
Read more on: Electronics, material, node, SoCs, transistorIBM builds ‘world’s smallest’ SRAM memory cell
IBM and its joint development partners, AMD, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE), have produced the first working static random access memory (SRAM) for the 22 nanometer (nm) technology node - the world’s first reported working cell built at its 300mm research facility in Albany, New York.
SRAM chips are precursors to more complex devices such as microprocessors. The SRAM cell utilises a conventional six-transistor design and has an area of 0.1um2, breaking the previous SRAM scaling barriers.
Dr TC Chen, vice president of Science and Technology, IBM Research, explained: “We are working at the ultimate edge of what is possible - progressing toward advanced, next-generation semiconductor technologies. This new development is a critical achievement in the pursuit to continually drive miniaturisation in microelectronics.”
22 nm is two generations away in chip manufacturing. The next generation is 32 nm — where IBM and its partners are in development with their 32 nm high-K metal gate technology.
Read more on: AMD, cells, chip, Electronics, IBM, nanometers, SRAM, transistorPaper-based transistor
Researchers from the Universidade Nova de Lisboa, have developed a Field Effect Transistor (FET) with a paper interstrate layer.
In a new approach, a common sheet of paper was used as the dielectric layer or oxide FETs. The researchers fabricated the devices on both sides of the paper sheet. This makes it act simultaneously as the electric insulator and as the substrate.
Electric characterisation of devices showed that the hybrid FETs performance outpace those of amorphous silicon TFTs, and rival the oxide thin film transistors (TFTs) produced on glass or crystalline silicon substrates. The results suggest promising new disposable electronics such as paper display, smart labels, RFID tags and bio-applications.
Read more on: Design, Electronics, FET, Silicon, TFTs, transistorHigh-performance low-power sensor at nanoscale
A high-performance, low-power silicon nanoscale sensor is being developed by engineers from The University of Southampton’s School of Electronics and Computer Science as part of a three-year European FP7-funded NEMSIC (Nano-electro-mechanical-system-integrated-circuits) project.
Project leader Professor Hiroshi Mizuta, and his team at ECS will co-integrate single-electron transistors (SETs) and nano-electro-mechanical systems (NEMS) on a single silicon technology platform to create a small, sensitve sensor with low-power consumption.
Read more on: Design, nanotechnology, NEM, sensor, Silicon, transistorNanotube device set to rival transistor-switched silicon-based memory
Researchers have produced a novel memory device set to rival transistor-switched silicon-based memory.
Conventional memory chips in electronic devices are made up of transistors, resistors and capacitors built in layers on a silicon wafer through a photolithographic process, during which precise patterns are etched on the silicon to form the chip. Today’s technology allows several million transistors to be built on a piece of silicon the size of a pinhead, but many researchers believe this form of memory has been pushed to its limits.
Researchers have been trying to create electromechanically driven switches small enough to rival transistor-switched silicon-based memory. Unlike transistors, electromechanically driven switches contain moving parts. Not only do electromechanical devices have excellent ON-OFF rations and fast switching characteristics, but the physical separation between the switch and capacitor in such devices means the data leakage problem is significantly reduced. However, until now, the technology has not been a viable alternative to silicon-based arrangements because it involved larger cells and more complex fabrication processes.
Professor Gehan Amaratunga and a team of international researchers have remedied these drawbacks by creating a novel nanoelectromechanical (NEM) switched capacitor based in vertically aligned multi-walled carbon nanotubes (CNTs).
Read more on: capacitor, electromechanically, Electronics, memory, nanotubes, NEM, Silicon, switch, transistor